The present disclosure relates to the field of multiprocessor based architectures for information handling systems, and more particularly to improving flexibility and reliability of the architecture.
As the value and use of information continues to increase, individuals and businesses seek additional ways to acquire, process and store information. One option available to users is information handling systems. An information handling system (‘IHS’) generally processes, compiles, stores, and/or communicates information or data for business, personal, or other purposes thereby allowing users to take advantage of the value of the information. Because technology and information handling needs and requirements vary between different users or applications, information handling systems may also vary regarding what information is handled, how the information is handled, how much information is processed, stored, or communicated, and how quickly and efficiently the information may be processed, stored, or communicated. The variations in information handling systems allow for information handling systems to be general or configured for a specific user or specific use such as financial transaction processing, airline reservations, enterprise data storage, entertainment, and/or global communications. In addition, information handling systems may include a variety of hardware and software components that may be configured to process, store, and communicate information and may include one or more computer systems, data storage systems, and networking systems.
A traditional dual processor based computer system architecture generally includes two separate integrated circuit (IC) chips for the two processors. The processors may be located on the same mother board or may be located on separate printed circuit boards connected by a communication bus. A dual core processor based computer system architecture generally refers to a single IC chip that includes two independently operable processors or cores. The dual core processor may or may not share components such as cache memory within the same IC chip. A multicore processor architecture may be considered as an extension of the dual core processor. That is, the multicore processor architecture includes more than two processors or cores on a single IC chip. A multicore, multiprocessor architecture typically includes a plurality of multicore processors that co-operate to perform one or more predefined functions. The plurality of multicore processors are coupled to each other and to one or more I/O devices via one or more communication links.
Use of commercially available chipsets for memory controllers to control memory, and input/output (I/O) hub (IOH) to connect various I/O devices coupled to a single processor as well as multiprocessor systems is well known. However, such chipsets may not accommodate desired features of multicore, multiprocessor based computer system architecture such as flexibility, performance and reliability. For example, number of communication links available to each IOH and to other multicore processors may be limited and/or be factory configured. This may limit implementation of certain topologies configured for predefined applications such as improved performance/throughput and fault tolerant operation. As another example, a first device plugged in a PCIexpress (PCIe) card slot coupled to a first IOH may not be able to communicate with a second device plugged in another PCIe card slot coupled to a second IOH located within the same system without compromising the number of PCIe slots and/or reliability of the architecture.
Therefore, a need exists to increase flexibility and reliability of multicore, multiprocessor architecture based systems. More specifically, a need exists to develop tools and techniques for dynamically reconfiguring topology of multicore, multiprocessor architecture based systems to meet predefined objectives such as minimizing impact of a single component failure and facilitating inter component communication. Accordingly, it would be desirable to provide for reconfiguring topology of multicore, multiprocessors included in an IHS, absent the disadvantages found in the prior methods discussed above.